1. Field of the Invention
The present invention relates to integrated circuits (IC) and, more specifically, to the transfer of hardware and software debug data off chip.
2. Description of the Related Art
FIG. 1 shows a block diagram of a prior-art debug testing configuration 100 for a conventional integrated circuit 102 having both ASIC (application-specific integrated circuitry) logic 104 and a programmable processor 106. In addition to IC 102, debug testing configuration 100 has a hardware logic analyzer 112, a trace port analyzer 114, and two monitors: hardware monitor 116 and software monitor 118. Hardware logic analyzer 112 is connected by X-lane bus 120 to input/output (I/O) pins 122 of IC 102, while trace port analyzer 114 is connected by Y-lane bus 124 to I/O pins 126 of IC 102.
Note that the number of I/O pins required by X-lane bus 120 and Y-lane bus 124 will depend on the type of signaling involved. For example, in differential signaling, each lane will have two pins, one for each half of the differential signal, while only one pin is required for single-ended signaling. In addition to the one or two pins per lane, additional pins may be required for power, ground, clock, and/or control signals associated with different sets of lanes.
As shown in FIG. 1, in addition to ASIC logic 104 and programmable processor 106, IC 102 includes trace logic 108, which captures information about the status of the processing implemented by programmable processor 106 so that the information can be analyzed and debugged off-chip. Trace logic blocks are commonly used in the art for creating software debug traces. Trace logic 108 may be based on the EMBEDDED TRACE MACROCELL™ (ETM) technology by ARM Ltd. of Cambridge, England.
During debug testing, trace logic 108 provides Y bitstreams of software debug data for transmission in parallel from IC 102 to trace port analyzer 114 via I/O pins 126 and bus 124. At the same time, ASIC logic 104 provides X bitstreams of hardware debug data for transmission in parallel from IC 102 to hardware logic analyzer 112 via I/O pins 122 and bus 120 to enable the processing of ASIC logic 104 to be analyzed and debugged off-chip.
During conventional debug testing of IC 102, it is often desirable to correlate the operations of ASIC logic 104 and programmable processor 106. This correlation can be achieved using active cross triggering, in which the detection of a particular event in one of the processing blocks is used to trigger the operations of the other processing block such that the operations of the two processing blocks will be correlated. For example, trace logic 108 and/or trace port analyzer 114 can be designed or programmed to (1) detect when a particular set of data is generated by programmable processor 106 or when a particular set of program code is executed by programmable processor 106 and (2) control the operations of ASIC logic 104 to implement appropriate functions such that the hardware debug data output by ASIC logic 104 will be correlated with the software debug data output by trace logic 108. As indicated by the broken lines shown in FIG. 1, this type of active cross triggering can be implemented either on-chip using trace logic 108 or off-chip using trace port analyzer 114 or both.
Alternatively, ASIC logic 104 and/or hardware logic analyzer 112 can be designed or programmed to (1) detect when a particular set of data is generated by ASIC logic 104 or when particular functions are executed by ASIC logic 104 and (2) control the operations of trace logic 108 and/or programmable processor 106 to implement appropriate functions such that the software debug data output by trace logic 108 will be correlated with the hardware debug data output by ASIC logic 104. As before, this type of active cross triggering can be implemented either on-chip using ASIC logic 104 or off-chip using hardware logic analyzer 112 or both.
Cross triggering can also be implemented in a passive mode in which hardware logic analyzer 112 and trace port analyzer 114 (1) monitor the hardware and software data, respectively, received from IC 102 and (2) communicate via off-chip link 128 to correlate the debug data generated by ASIC logic 104 and programmable processor 106 without actively controlling the operations of either processing block.
Note that, in alternative embodiments, an integrated circuit can have two or more different blocks of ASIC logic and/or two or more different programmable processors. In such cases, the detection of an event in any one processing block (e.g., in either an ASIC logic block or a programmable processor) can be used to trigger operations related to two or more different processing blocks, including combinations of one or more ASIC logic blocks and one or more programmable processors.
In any case, hardware logic analyzer 112 and trace port analyzer 114 process the hardware and software debug data, respectively, received from IC 102 to generate appropriate hardware and software debug displays for rendering on hardware and software monitors 116 and 118.
A certain number of I/O pins on IC 102 are required to support the debug testing of ASIC logic 104 and programmable processor 106. As integrated circuits become more sophisticated, the amount of data required to perform such debug testing increases, resulting in larger values for X and Y and therefore the utilization of more I/O pins for debug testing. The resulting higher pin counts increase IC manufacturing difficulty and cost.